View L3000SX-77_1088283.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

l3000s l3030 june 1997 subscriber line interface kit preliminary data . programmable dc feeding resis-tan- ce and limitingcurrent (fourvalues avai- lable) . three operating modes : stand-by, conversation, ringing . normal/boostbattery, direct/rever- se polarity . signalling function (off-hook/gnd-key) . filtered off-hook detection in stand-by (10ms) . quick off-hook detection in conver- sation (< 1ms) for low dial pulse de- tection distortion . hybrid function . ringing generation with quasi zero output impedance, zero crossing in- jection (no ext. relay needed) and ring trip detection . automatic ringing stop when off- hook is detected . parallel and serial digital interfa- ces . teletaxe signalinjection (2v rms /5v rms ) . low number of external compo- nents . good rejection of the noise on bat- tery voltage (20db at 10hz and 35db at 1khz) . possibility to work also with high common mode currents . integrated thermal protection with thermal overload indication . surface mount package (plcc44 + powerso-20) description plcc44 flexiwatt15 the st slic kit (l3000s/l3030) is a set of solid state devices designed to integratemain of the fun- ctions needed to interface a telephone line. it con- sists of 2 integrated devices : the l3000s line interface circuit and the l3030 control unit. this kit performs the main features of the borsht functions : - battery feed - ringing - signalling - hybrid additional functions, such as battery reversal, extra batteryuse, line overvoltagesensing and metering- pulse injection are also featured ; most external characteristics,as ac and dc impedances,are pro- grammable with external components.the slic in- jects ringing in balanced mode and for that, as well as for the operation in battery boosted, a positive battery voltage shall be available on the subscriber card. as the right ringing signal amplification both in voltage and in current is provided by slic, the ring signal generatorshall onlyprovide a low level signal (0.285vrms). this kit is fabricated using a 140v bipolar technolo- gy for l3000sand a 12v bipolar i 2 l technologyfor l3030. l3030 is available plcc44 and l3000s in both flexiwatt15 and powerso-20 for surfacemount application. this kit is suitable for all the following applications: c.o. (centraloffice),dlc (digital loopcarrier) and high range pabx (private automatic branch ex- change). powerso20 slug-up slug-down ordering numbers : l3030 (plcc44) l3000sx-vm (flexiwatt15) l3000sx (powerso20 slug-up) L3000SX-77 (powerso20 slug-down) 1/29
pin connections (top view) plcc44 flexiwatt15 v b- v bim agnd tip mnt bgnd v b+ v dd v in n.c. v b- 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 v b- d97tl290 ref c1 it c2 il n.c. ring v b- powerso-20 (slug-down) v b- v bim v in v dd bgnd mnt v b+ tip n.c. ring n.c. il c2 it c1 ref agnd v b- 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 v b- v b- d94tl125 powerso-20 (slug-up) l3000s - l3030 2/29
pin description (l3000s) flex. n pso n name description 1 3 tip a line termination output with current capability up to 100ma (i a is the current sourced from this pin). 2 4 mnt positive supply voltage monitor 35v b + positive battery supply voltage 4 6 bgnd battery ground relative to the v b + and the v b supply voltages. it is also the reference ground for tip and ring signals. 57v dd positive power supply + 5v 6 8 vin 2 wire unbalanced voltage input. 7 9 vbim output voltage without current capability, with the following functions : - give an image of the total battery voltage scaled by 40 to the low voltage part. - filter by an external capacitor the noise on v b . 81,10 11, 20 v b negative battery supply voltage 9 12 agnd analog ground. all input signals and the v dd supply voltage must be referred to this pin. 10 13 ref voltage reference output with very low temperature coefficient. the connected resistor sets internal circuit bias current. 11 14 c1 digital signal input (3 levels) that defines device status with pin 12. 12 15 c2 digital signal input (3 levels) that defines device status with pin 11. 13 16 i t high precision scaled transversal line current signal. i t = i a + i b 100 14 17 i l scaled longitudinal line current signal. i l = i b - i a 100 15 19 ring b line termination output with current capability up to 100ma (i b is the current sunk into this pin). 2, 18 n.c. not connected notes: 1) unless otherwise specified all the diagrams in this datasheet refers to the flexiwatt15 pin connection. 2) all informations relative to the powerso-20 package option should be considered as advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. l3000s - l3030 3/29
pin description (l3030) pin symbol function 1 tst this pin is connected internally for test purpose. it should not be used as a tie point for external components. 2 ref bias set 3 agnd analog ground 4 vss 5v 5 vdd + 5v 6 n.c. not connected. 7 czs ac feedback input 8 acf ac line impedance synthesis 9 zac ac impedance adjustement 10 11 12 tst these pins are connected internally for test purpose. it should not be used as a tie point for external components. 13 vout two wire unbalanced output. 14 cm capacitor multiplier input 15 rc dc feedback input 16 it transversal line current 17 rdc dc feeding system 18 eia read/write command 19 ncs chip select command 20 dio data input/output 21 dckl clock signal 22 dgnd digital ground 23 n.c. not connected. 24 n.c. not connected. 25 n.c. not connected. 26 ci input/output changing command 27 c1 state control signal 1 28 c2 state control signal 2 29 n.c. not connected. 30 n.c. not connected. 31 il longitudinal line current 32 crts ringtrip det. & ttx shaping 33 ttxin teletaxe signal input 34 rgttx ttx filter level compensation 35 ttxf ttx filter input 36 zb balancing network 37 38 39 tst these pins are connected internally for test purpose. it should not be used as a tie point for external components. 40 tx 4w sending output 41 rx/rg 4w receiving and ring input 42 vbim battery image input 43 44 tst these pins are connected internally for test purpose. it should not be used as a tie point for external components. l3000s - l3030 4/29
l3000s block diagram l3030 block diagram l3000s - l3030 5/29
absolute maximum ratings symbol parameter value unit v b negative battery voltage 80 v v b + positive battery voltage 80 v |v b | + |v b +| total battery voltage 140 v v dd positive supply voltage + 6 v v ss negative supply voltage 6 v v agnd v bgnd max. voltage between analog ground and battery ground 5 v t j max. junction temperature + 150 c t stg storage temperature 55 to + 150 c operating range symbol parameter min. typ. max. unit t oper operating temperature range 0 70 c v b negative battery voltage 70 48 24 v v b + positive battery voltage 0 + 72 + 75 v v b +v b + total battery voltage 120 130 v v dd positive supply voltage + 4.5 + 5.5 v v ss negative supply voltage 5.5 4.5 v i max total line current (il + it) 85 ma thermal data symbol parameter value unit l3000s high voltage flexiwatt pwso20 r th j-case thermal resistance junction to case max. 4 typ. 2 c/w r th j-amb thermal resistance junction to ambient max. 50 max. 60 c/w l3030 low voltage r th j-amb max. resistance junction to ambient 80 c/w functional description l3000s - high voltage circuit the l3000slineinterfaceprovidesa batteryfeeding for telephonelines and ringing injection.the ic con- tains a state decoderthat underexternal controlcan force the following operational modes : stand-by, conversation and ringing. in addition power down mode can be forced con- necting the bias current resistor to v dd or leaving it open. two pins, i l andi t , carryout the information concer- ning line statuswhich is detectedby sensing the line current into the output stage. the l3000s amplifies both the ac and dc signals entering at pin 6 (vin) by a factor equal to 40. separate grounds are provided : - analog ground as a reference for analog signals - battery ground as a reference for the output sta- ges the two ground should be shorted togetherat a low impedance point. l3030 - control unit the l3030 low voltage control unit controls l3000s line interface module, giving the proper information to set line feed characteristic, to inject ringing and ttx signal and synthetizes the line and balance im- pedances. an on chip digital interface allows a mi- croprocessor to control all the operations. l3030 defines working states of line interface and also in- forms the card controller about line status. l3000s - working states in order to carry out the different possible opera- tions, the l3000s has several different working sta- tes.each stateis definedby the voltagerespectively applied by pins 27 and 28 of l3030 to the pins 11 and 12 of l3000s. three different voltage levels ( 3, 0, + 3) are avai- lable at each connection, so defining nine possible l3000s - l3030 6/29
table 1. pin 28 of l3030 / pin 12 of l3000s (c2) +3 0 3 pin 27 of l3030 pin 11 of l3000s + 3 stand-by conversation in normal battery direct polarity conversation in normal battery reverse polar 0 not allowed. conversation in boost battery direct polarity conversation in boost battery reverse polar 3 not allowed. ringing with direct polarity not allowed. states as listed in table. 1. appropriate combinations of two pins define the three modes of the st slic, that are : a) stand-by (sby) b) conversation (cvs), normal and reverse pola- rity c) ringing (ring) d) boost battery (bb), normal and reverse polarity a fifth status, power down (pd), can be set discon- necting the bias resistor (rh) from pin 10 ofl3000s by means of an external transistor. the main difference between stand-by and power down is that in sby the power consumption on the voltage battery vb ( 48v) is reduced but the l3000s dc feeding and monitoring circuits are still active. in pd the power consumption on vb- is re- duced to zero, and the l3000s is completely swit- ched off. the sbystatus shouldbe used when the telephone is in on hook and pd status onlyin emergencycon- dition when it is mandatory to cut any possible dis- sipation but no operation are requested. operating modes stand-by (sby) mode in this mode, the bias currents of both l3000s and l3030are reducedas only someparts of the two cir- cuits are completely active, control interface and current sensors among them. the current supplied to the line is limited at 7ma, and the slope of the dc characteristic corresponds to : r = 2 3 x ( rfs + 2rp ) the line voltage in on hook conditionisjust the bat- teryvoltage minus the voltage drop (approx. 15v)of the output stage amplifiers (see fig. 1). figure 1 : dc characteristics in stand-bymode. l3000s - l3030 7/29
the ac characteristic is just the resistance of the two serial resistors rp. in stand-bymode the batterypolarity is just in direct condition,that is the tip wire more positive than the ring one ; boost battery is not achievable. there are two possible line conditions where the slic is expected to be in stand-by mode : 1) on-hook (i line < 5ma). normal on-hook condition. 2) off-hook (i line > 7ma). handset is unhooked, the slic is waiting for command to activate conversation. when the slic is in stand-by mode, the power dis- sipation of l3000s does not exceed 120mw (from -48v) eventually increased of a certain amount if some current is flowing into the line. the power dissipation of l3030 in the same condi- tion, is typically 120mw. the stand-bymode is set when the byte sent to the l3030 serial digital interface has the first two bits (bit0r and bit1r) equal to o0o. settingto 0 all the 8 bits of the command sent to the digital interface of l3030, the bias currents of both l3000s and l3030 are reduced and only some parts of the two circuits are active similarly to the stand-by mode ; in this situation, named power- down denial, the line sensors are disabled (on/off-hook line conditions cannot be recogni- zed) and the current supplied to the line is limited at 0.25ma. conversation (cvs) or active mode in conversationmodeit is possibleto selectbetween two different dc characteristics by the bit5r of the serial interface. 1) normal battery (nb) 2) boost battery (bb) it is also possibleto select(bit4r)the polarity of the dc line voltage and (bit6r-bit7r) one of the four values of limiting current (25ma or 30ma or 45ma or 70ma). battery reverse can take place either before or du- ring conversation. as far as the dc characteristic in normal battery is concerned, three different feeding conditions are present : a) current limiting region ; the dc impedance of the slic is very high (> 20 kohm) and therefore the systemworkslike a currentgenerator,the current value being set through the digital interface (25/30/45/70ma). b) standard feeding system region ; the characteristic is equal to a 48v ( 60v) battery (note 1), in series with two resistors, whose value is set by external components (see external component list of l3030). c) low impedance region ; the battery value is reducedto 33v (45v) and the serial resistance is reduced to the value specified in stand by mode, that is : 2 3 x ( rfs + 2rp ) switching between the three region is automaticwi- thout discontinuity, and depends on the loop resi- stance.fig. 2 shows the dc characteristic in normal battery condition. when the boostbatteryconditionisactivatedthe low impedance region can never be reached by the sy- figure 2 : dc characteristic (n.b.) i lim = 25/30/45/70ma. note : 1. this value of voltage battery, named apparent battery, is fixed internally by the control unit and is independent of the actual battery value. so, the voltage drop in the low impedance region is 15v. it is also possible to increase up to 25v this value setting bit3r to 1. l3000s - l3030 8/29
stem ; in this case the internal dropout voltage is equal to 30v. fig. 3 shows the dc characteristic in boost battery condition. in conversationmode, on request of controlproces- sor, whatever condition is set (normal or boost bat- tery, direct or reverse polarity), you can inject the 12khz(or16khz)signal (permanentlyapplied at the pin 33 with 950mvrms typ. amplitude), as metering pulses. a patented automatic control system adjust the level of the metering signal, across the line, to 2vrms setting bit3 = 0, or to 5vrms setting bit3 = 1 ; this, regardless of the line impedance. moreover the metering signal is ramped at the beginningand at the end of each pulse to prevent undesirableclic- king noise ; the slope is determined by the value of cint (see the external component list of l3030). the slic also provides, in the transmit direction (fromline to 4-wire side), an amplifier to insert an ex- ternal notch filter (series resonator) for suppressing the 12/16khz residual signal. fig. 4 shows a suggestednotch filter configuration. the metering pulses can be injected with a dc line current equal to zero (on-hook operation). if teletax is not used the notch filter can be replaced by a 1k w resistor. inconversationmode theac impedanceat the line ter- minals,zml,issynthetizedby theexternalcomponents zac and rp, according to the following formula : zml = zac + (rp1 + rp2) depending on the characteristic of the zac network, zml canbe eithera pure resistance or a complex im- pedance,so allowing st slictomeetdifferentstand- ards as far as the return loss is concerned. the capacitor ccomp guaranteesstability to the system. the two-to-four wire conversion is achieved by me- ans of a wheatstone bridge configuration,the sides of which being : 1) the line impedance (zline), 2) the slic impedance at line terminals (zml), 3) thenetworkza connectedbetweenpin 36 and 41 of l3030 (see externalcomponentlist of l3030), 4) the network zb between pin 36 and ground that shall copy the line impedance. for a perfectbalancing,the following equationshall be verified : za zb = zml zline it is important to underline that za and zb are not obliged to be equal to zml and to zline, but they both may be multiplied by a factor (up to ten) so al- lowing use of smaller capacitors. inconversation,the l3000sdissipatesabout250mw foritsownoperation; thedissipationdependingon the current supplied to the line shall be added. the fig 5 and fig 6 show the dc characteristicfor two different feeding resistance. 2 x 200 ohm and 2 x 400 respectively. f = 1 2 p ```` lxc l = r2 x r4 x r5 r3 xc2 figure 4 : externalteletaxe filter. figure 3 : dc characteristic (b.b.) i lim = 25/30/45/70ma. l3000s - l3030 9/29
figure 5 : dc characteristic for 2 x 200 ohm feeding system. figure 6 : dc characteristic for 2 x 400 ohm feeding system. figure 7 : line current versus loop resistance, rfs = 200 w ,r p =30 w ,v b = 48v. l3000s - l3030 10/29
ringing mode when ringingis selected (bit2r= 1,bit0r = 0), the control unit l3030 presets the l3000s to operate between 48v ( 60v) and + 72v (+ 60v) battery. then,settingbit1 =1, a low levelsignal(0.285vrms with frequency range 16-66hz) applied to pin 41, is amplified and injected in balancedmode to the line throughl3000s with a superimposeddc voltageof 24v. the impedance to the line is given by the two external resistors and the 24v dc polarity can only be direct. the first and the lastringing cycles aresynchronized by l3030 so that ringing always starts and stops at zero crossing. ring trip detection is performed au- tonomouslyby the slic,without anyparticularcom- mand, using a patented system ; when handset is lifted, slic suspends the ringing signal just remai- ning inthe ringingmode. inthiscondition,the control unit l3030 checks that the loop is closed for a time equal to two periods of the ringing signal ; if the clo- sure is confirmed, a flag (bit0t = 1) is set and the slic waits the new command from the control pro- cessor. whereas the loop closure is not confirmed, the ringing signalis newly applied to theline, without setting bit0t. digital interface functional description the l3030 states and functions are controlled by central processor through five wires defining a digi- tal interface.it is possibleto select the interfacewor- king mode between serial or parallel (pin 33 tied to a voltage between 4 and 5v). 1) serial mode the five wires of the digital interface have the follo- wing functions : - clock (dclk), entering at pin 21 - data in/data out (dio), exchanged at pin 20 - input/outputselect (eia), entering at pin 18 - chip select (ncs), entering at pin 19 - change ncs from in to out (ci), entering at pin 26 (note 1) the maximum clock frequency is 600khz. when eiasignal is low data are transferred from the card controller into i/o registers of the l3030 selec- ted by ncs signal tied at low level ; then data are latched for execution.in this phasea complete 8 bit word is loaded into internalregister and consequen- tly ncs signal must remain low for the correspon- ding 8 clock pulses (dclk). the eia signal must remain at low level at least for the time in whichncs signal remain low. the device load data in input re- gister during the positive edge of clock signal (dclk) and store the contents of the register on the positive edge of ncs signal. when eia signal is high data are transferred from the l3030 selected by ncs tied to low level to the card controller. the l3030 status is described by five bits contained in the output register ; the ncs signalcan remain low for fiveor lessclockpulsesde- pending if the card controller want to read the com- plete l3030 status or only a part of it. fig. 8, 9 showthe completewrite and read operation timing. table 1 shows the meaning of each bit of an i/o data. l3000s - l3030 11/29
table 1 : serial mode. meaning value data in (note 2) bit0r = impedance (note 3) 0 - stand-by/ringing 1 - conversation bit1r = ttx & ring timing (note 4) 0 - timing off 1 - timing on bit2r = ring (note 5) 0 - ttx signal injection 1 - ring signal injection bit3r = ttx level 0 - low amplitude (2v rms ) 1 - high amplitude (5v rms ) bit4r = battery polarity 0 - normal polarity 1 - reverse polarity bit5r = extra feeding 0 - normal battery 1 - boosted battery bit6r bit7r current limiting 0 25ma 0 0 30ma 1 1 45ma 1 1 70ma 0 data out (note 6) bit0t = line supervision 0 - on hook 1 - off hook bit1t = ground key 1 - long. line current < 17ma 0 - long. line current > 17ma bit2t = internal line current limiter (note7) 0 - off 1-on bit3t = line voltage 0 - normal 1 - minus of half battery bit4t = thermal overload (note 8) 1 - off 0-on notes : 1. when ci signal is tied to low level, ncs signal is the chip select input ; with ci signal at high level, the ncs signal becomes an output that carry out the logical sum of the following bits : bit0t, bit1t. 2. the description of the commands is referred to the system l3030 + line interface module. 3. to set sby mode with i lim = 7ma : bit0r = 0 and at least one of the two last bits (bit 6r ; bit7r) must be set to 1. 4. ttx and ring signals are injected into the line interface module with bit1r to o1o. 5. to set ring mode at least one of the three last bits (bit5r, bit6r, bit7r) must be set to 1, in addi tion bit0r must be set to 0. 6. the description of the commands is referred to the system l3030 + line interface module. 7. the bit bit2t is set to 1 when the slic is operating in conversation mode and into the limiting curr ent region (short loop). 8. the bit bit4t is set to 1 when the junction temperature of l3000s is about 140 c. l3000s - l3030 12/29
figure 8 : writing operation timing (serial mode). figure 9 : reading operation timing (serial mode). l3000s - l3030 13/29
2) parallel mode this operating mode is enabled connecting pin 33 to a voltagein the rangefrom 4v to 5v. thefive wire have the following functions : - power down/feeding (eia), entering at pin 18 - timing (ci), entering at pin 26 - ring (dclk), entering at pin 21 - on-hook/off-hook(ncs), outgoing at pin 19 - ground-key (dio), outgoing at pin 20 in this operating mode the signals at the inputs are immediately executed,without any external clock ti- ming ; all the internalregisters are bypassed.the in- formations sent back on pins 19 and 20, display in real time the setting of internal circuits, that means line status. in the table 2 the correspondence bet- ween the interface wires in the parallel mode and equivalent bit in serial mode is pointed out ; where there isn't this correspondence, the internal setting is shown. table 2 : parallel mode. pin rif. meaning (note 1) eq. bit of ser. interf. value 18 eia pd/feeding bit0r 0 : high impedance 1 : low impedance 26 ci timing bit1r 0 : ring timing off 1 : ring timing on 21 dckl ring bit2r 0 : no ring 1 : ring injection bit3r 0 : low amplitude bit4r 0 : normal polarity bit5r 0 : normal battery bit6r 0 : 1: line curr. = 30ma bit7r 19 ncs on-hook/off-hook bit0t 0 : on-hook 1 : off-hook 20 dio ground key bit1t 1 : long. curr. < 17ma 0 : long. curr. > 17ma bit2t bit3t bit4t note : 1. the description of the commands is referred to the system l3030 + line interface module. digital interface electrical characteristics (v dd =+5v,v ss = 5v, t amb .=25 o c) (refer to plcc44 package) symbol parameter test conditions min. typ. max. unit static electrical characteristics vil input voltage at logical o0o pins 18, 19, 20, 21, 26 0 0.8 v vih input voltage at logical o1o 2.0 5 v iil input current at logical o0o vil = 0v 200 m a iih input current at logical o1o vih = 5v 10 m a vol output voltage at logical o0o pins 19, 20 iout = 1ma 0.4 v voh output voltage at logical o1o pins 19, 20 iout = 1ma 2.4 v ilk tristate leak. current pin 20 ncs = o1o 10 m a l3000s - l3030 14/29
digital interface electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit dynamic electrical characteristics fclk clock frequency 1 600 khz tr, tf clock rise and fall time 50 ns twh, twl clock impulse width 750 ns tis ci to ncs set up time 300 ns tec o0o eia to dckl set up time 300 ns tsc dckl to ncs delay (+ edge) 300 ns tsd data in set up time 0 ns thd data in hold time 800 ns tcs ncs to dckl hold time 800 ns tca o0o eia to dckl hold time 900 ns tac o1o eia to dckl set up time 400 ns tzd data out to o0o ncs delay 0 600 ns tce o1o eia to dckl hold time 900 ns tdz data out to o1o ncs delay 500 ns tdd data out to dckl delay 1500 ns tsi o0o ci to ncs hold time 300 ns operation description to set slic in operation the following parameters have to be defined : - the dc feedingresistance rfs, definedas the re- sistance of each side of the traditional feeding sy- stem (most common values are 200, 400 or 500 ohm). - the ac impedanceat line terminals, zml, to which the return loss measurement references.it can be real (typically 600 ohm) or complex. - the equivalent ac impedance of the line zline, when evaluating the trans hybrid loss (2/4 wire conversion). it is usually a complex impedance. - the ringing signal frequency fr (st slic allows frequency ranging from 16 to 66hz). - the metering pulse frequency ft (two values are possible : 12khz or 16khz). - the value of the two resistors rp1/rp2 in series with the line terminals ; main purpose of the a.m. resistors is to allow primary protection to fire. st suggest the minimum value of 50 ohm for each side. on this assumptions,the following componentlistis defined. l3000s - l3030 15/29
external component list for the line interface pin component involved parameter or function ref. value l3000s 10 rref 24.9k w 1% bias resistance 1,15 rp 30 to 100 w line series resistor 7 cdvb 47 m f 20v battery voltage rejection 3 cvb+ 0.1 m f 100v (1) positive battery filter 8 cvb 0.1 m f 100v (2) negative battery filter 8 d1 bat 49x protective shottky diode l3030 (plcc44) 4-3 cvss 0.1 m f 15v negative supply voltage filter 5-3 cvdd 0.1 m f 15v positive supply voltage filter 7-8 rr 16k w (range: 10 to 50k w) capacitor multiplier gain (8) 15-17 rdc 2 x (rfs rp1) dc feeding resistor (rdc > 270 w ) 7-15 cac1 (3) 1 6.28 x 250 x ( zac + rdc ) ac path decoupling 14-15 cac2 cac1 8-9 zac zml (rp1 + rp2) 2 wire ac impedance 8-9 ccomp 1/(6.28 x 150000 x (rpc)) ac loop compensation 9-14 rpc rp1 + rp2 rp insertion loss compensation 2-3 rref 24.9k w 1% bias resistance 36-3 zb k x zline (note 4) line impedance balancing network 36-41 zl k x rpc in series with k x zac // (ccomp/k) slic impedance balancing network (note 5) 32-3 cint (note 6) ring trip detection time constant 15-16 ccon 0.15 m f (note 7) interface time constant 35 ttx filt. z ttx =1k w 1% in speech band z ttx 0 w at ttx freq. (note 9) teletax filter. 34 r gttx 10k w 1% teletax filter. notes : 1. in case line cards with less than 7 subscribers are implemented cvb capacitor should be equal to 680nf/n where n is the number of subscriber per card. 2. this shottky diode or equivalent is necessary to avoid to damage to the device during hot insertion or in all those cases when a proper power up sequence cannot be guaranteed. in case the shottky diode is not implemented the power sequence should guarantee that vb+ is always the last supply applied at power on and the first removed at power off. in case an other shottky diode type is adopted it must fulfil l the following characteristics: v f < 450mv @ i f =n ? 15ma, t amb =25 c v f < 350mv @ i f =n ? 15ma, t amb =50 c(t jl3000 =90 c) v f < 245mv @ i f =n ? 15ma, t amb =85 c(t jl3000 = 120 c) where n is the number of line sharing the same diode. 3. if the internal capacit y multiplier stage is not used, pin 7 must be connected with pin 14 without mounting rr and cac2. in this case cac1 = 1/(6.28 x 30 x rdc). 4. the structure of this network shall copy the line impedance, in case multiplied by a factor k = 1....10 5. k as fixed at note 4. 6. cint can have the following values : 7. ccon is necessary to work owit hout on/off hook detection-errorso during ttx-pulses. 8. rr is used by a capacitor multiplier circuit to synthetize an higher ac/dc splitting capacitor starting from cac1 and cac2. supposing cac1 = cac2 = cac the synthetized capacitor value will be equal rr + zml zml ? cac. 9. if teletax is not used the ttx filt. can be replaced by a 1k w resistor. fr. (hz) 16/18 18/21 21/26 26/31 31/38 38/46 46/57 57/66 cint (nf) 560 470 390 330 270 220 180 150 l3000s - l3030 16/29
figure 10 : typical application schematic diagram. figure 11 : typical application schematic diagram without capacitor multiplier. l3000s l3000s l3000s - l3030 17/29
electrical characteristics (refer to the test circuits of the figure 12, v dd = + 5v, v ss =- 5v, v b +=+72v,v b = 48v, t amb =+25 o c, ttx filt = 1k w ) symbol parameter test conditions min. typ. max. unit stand-by vls output voltage at l3000s terminals iline = 0ma iline = 5ma 30.0 28.2 40.0 38.5 v v ilcc short circuit current data in (note 1) 000x00x1 5 8.5 ma iot on/off-hook detection threshold 5 8.5 ma vls symmetry to ground iline = 0ma .75 v stand by denial ilcc short circuit current data in 000x00x0 2 ma dc operation - normal battery (v ttx =2v rms , low level) vlo output voltage at l3000s terminals ilim = 70ma data in 1000x010 iline = 0ma iline = 20ma iline = 50ma 31.0 24.0 2.5 35.0 28.8 17.5 v v v ilim current programmed through the digital inter. 10% ilim + 15% ma io on-hook detection threshold 8 ma if off-hook detection threshold 12 ma ilgk longitudinal line current with gk detect 10 17 26 ma dc operation - boost battery vlo output voltage at l3000s terminals iline = 0ma iline = 20ma 86 68.6 95.6 81 v v ac operation ztx sending output impedance 4 wire side 10 w zrx receiving input impedance 4 wire side 100 k w thd signal distorsion at 2w and 4w terminals 0.5 % r1 2w return loss f = 300 to 3400hz 22 db thl trans hybrid loss f = 300 to 3400hz 24 db gs sending gain vso = 0dbm f = 1020hz norm. polarity 0.25 + 0.25 db gsf sending gain flatness versus frequency f = 300 to 3400hz respect to 1020hz 0.1 + 0.1 db gsl sending gain linearity fr = 1020hz, vsoref = 10dbm vso = + 4 / 40dbm 0.1 + 0.1 db gr receiving gain vri = 0dbm f = 1020hz norm. polarity 0.25 0 + 0.25 db grf receiving gain flatness f = 300 to 3400hz respect to 1020 0.1 + 0.1 db notes : 1. the data into the digital interface of l3030 are send in serial mode. the format of data is the following : a) data in : the bit at left side is bit 0 of the writing word, while the bit at the right side is b it 7. b) data out : the bit at the left side is bit0 of the reading word, whil e the bit at the right is bi t4. when appear a symbol x, the value of the bit don't care. l3000s - l3030 18/29
electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit ac operation (continued) grl receiving gain linearity fr = 1020hz, vriref = 10dbm vri = + 4 / 40dbm 0.1 + 0.1 db np4w psophometric noise at 4w-tx terminals 75 70 dbmp np2w psophometric noise at line terminals 75 70 dbmp svrr supply voltage rejection ratio relative to vb f = 3400hz 30 db svrr relative to v dd f = 3400hz vs = 100mvrms 30 26 db svrr relative to v ss 32 30 db ltc longitudinal to transversal conversion f = 300 to 3400hz iline = 30ma, zml = 600 w 49 (1) 60 db tlc transversal to longitudinal conversion 48 51 db td propagation time both direction 40 m s tdd propag. time distortion 25 m s vttx line voltage of teletaxe signal v ttxin = 950mvrms note 2 note 3 1.7 4.5 2.3 5.5 v v thd teletaxe signal harmonic dist. ttx filt = 0 w @ 16khz note 4 5% zitt teletaxe amplif. input impedance pin 33 of l3030 100 k w ac operation boost battery gs sending gain vso = 0dbm f = 1020hz norm. polarity 0.66 0.16 + 0.34 db gr receiving gain vri = 0dbm f = 1020hz norm. polarity 0.27 + 0.08 + 0.43 db np4w psophometric noise at 4w-tx terminals 73 68 dbmp np2w psophometric noise at line terminals 73 68 db svrr relative to vdd f = 3400hz vs = 100mvrms 23 db svrr relative to vss 23 db ringing phase vlr superimposed dc voltage rloop > 100k w rloop = 1k w 19 17 23 21 27 25 v v vacr ringing signal at line termin. rloop = 1k w /1 m f 56 vrms if dc off-hook det. threshold 1.5 3.5 ma ilim current limit. 85 130 ma vrs ringing simmetry 2 vrms thdr ringing signal distortion v ac = 0.285v rms f ring = 30hz 5% notes : 1. up to 52db using selected l3000s. 2. the configuration of data sent to device change, every 100ms, from - 1100x010 - to - 1000x010 - 3. the configuration of data sent to device change, every 100ms, from - 1101x010 - to - 1001x010 - 4. error generated by ttx filt 0 ohm, on the output teletax amplitude is err% = 100 x (1 + a) x b/c where a = 10 kohm/rgttx[kohm], b = tt xfilt[kohm], c = (ttxfilt[kohm] + 1 kohm), for example 10 ohm means err% = 2 %. l3000s - l3030 19/29
electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit ringing phase zir ringing amplif. input impedance pin 41 of l3030 100 k w vrr residual of ringing signal at tx output 600 mv trt ring trip detection time fring = 16hz t = 1/fring (1t) 125 (2t) ms toh off-hook status delay after the ringing stop 125 (2t) ms trs cut off of ringing ring trip not confirmed 188 (3t) ms supply current idd positive supply current cs = 1 stand-by conversation (nb/bb) ringing 16.0 26.0 16.5 20.0 31.0 21.0 ma ma ma iss negative supply current cs = 1 stand-by conversation (nb/bb) ringing 9 19 9 12 23 12 ma ma ma i bat negative battery supply current line current = 0ma stand-by conversation nb conversation bb ringing 2 5 6.6 14 2.5 6.5 8.0 17 ma ma ma ma i bat+ positive battery supply current line current = 0ma stand by conversation nb conversation bb ringing 10 10 8 12 15 15 10 13.5 m a m a ma ma nb = normal battery bb = boosted battery figure 12 : slic test circuit schematic. l3000s l3000s - l3030 20/29
32 crts zb 36 zb za cint rx 41 czs 7 acf 8 ccomp zac rpc zac 9 cm 14 to/from card controller 15 rc 17 rdc rdc 18 19 eia ncs 20 21 dio dclk 26 ci it 16 c con c1 27 c2 28 il 31 vout 13 vbim 42 rgttx 34 vss 4 l3030 cac1 ttx filter rgttx ttxf 35 vdd 5 ref 2 33 40 3 rl cvss vss cvdd 5 9 cdvb rh vdd agnd ref 10 7 6 14 12 11 13 vbim vin il c2 c1 it vdd l3000n 43 bgnd vb+ bgnd vb+ vb- 8 1 tip ttxin tx agnd cvb- cvb+ d1 20 w vb- 30 w 2 15 20 w 30 w l3121 ctl (*) vring= 285mvrms 26 il0 il2 25 7 6 24 23 15 il1 il3 il4 il5 mr 2 vfro v cc 100nf 28 +5v -5v 100nf 100nf dx0 dx1 tsx0 tsx1 fsx bclk fsr dr0 dr1 cs cclk co ci mclk 18 19 20 21 22 16 8 10 9 14 13 11 12 17 ts5070 gnd v ss mnt ring 3 l3121 22nf 22nf bgnd 2 1 4 1 2 3 4 vb+ vb- (*) the analog multiplexer can be avoided if the v ring = 285mv rms is provided by the codec. d94tl126 figure 13: typical application schematic with 2 nd generation combo. l3000s l3000s - l3030 21/29
32 crts zb 36 zb za cint rx 41 czs 7 acf 8 ccomp zac rpc zac 9 cm 14 to/from card controller 15 rc 17 rdc rdc 18 19 eia ncs 20 21 dio dclk 26 ci it 16 c con c1 27 c2 28 il 31 vout 13 vbim 42 rgttx 34 vss 4 l3030 cac1 ttx filter rgttx ttxf 35 vdd 5 ref 2 33 40 3 rl cvss vss cvdd 5 9 cdvb rh vdd agnd ref 10 7 6 14 12 11 13 vbim vin il c2 c1 it vdd l3000n 43 bgnd vb+ bgnd vb+ vb- 8 1 tip ttxin tx agnd cvb- cvb+ d1 20 w vb- 30 w 2 15 20 w 30 w l3121 ctl (from card contr.) (**) vring= 285mvrms vfxi+ vfro v cc c +5v -5v 100nf 100nf dx dr tsx mclkx mclkr/ bclk bclkr/ fsr fsx etc5057 gnda v ss mnt ring 3 l3121 22nf 22nf bgnd 2 1 4 1 2 3 4 vb+ vb- (*) resistors r1 to r4 program ix/rx gains za, zb shold be >>than r2. (**) the analog multiplexer can be avoided if the v ring = 285mv rms is provided by the codec. d94tl127a (*) r4 r3 r1 r2 gsx vfxi- figure 14: typical application schematic with 1 st generation combo. l3000s l3000s - l3030 22/29
test circuits figure 1 : symmetry to ground. r l = 20 log | z l - z| |z l + z | = 20 log |2 v s | |e| 1 wc << z figure 2 : 2w return loss. appendix slic test circuits referring to the test circuit reported at the end of each slic data sheet here below you can find the proper configuration for each measurement. in particular : a-b : line terminals c : tx sending output on 4w side d : rx receiving input on 4w side e : ttx teletaxe signal input r gin : low level ringing signal input. thl = 20 log 10 |v s | |v r | figure 3 : trans-hybrid loss. g s = 20 log 10 |v r | |v so | figure 4 : sendinggain. l3000s - l3030 23/29
g r = 20 log 10 | v r | | v s | figure 5 : receiving gain. test circuits (continued) svrr = 20 log | v n | | v r | figure 6 : svrr relative to battery voltage vb. l t = 20 log |v r | |e | figure 7 : longitudinalto transversal conversion. t l = 20 log 10 | v r | |v s | figure 8 : transversal to longitudinal conversion. figure 9 : ttx level at line terminals. figure 10 : ringing simmetry. l3000s - l3030 24/29
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 l3000s - l3030 25/29
flexiwatt 15 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 5.00 0.196 b 1.90 0.074 b1 0.1 0.004 d 4 (typ.) e 0.30 0.012 f 0.90 0.035 f1 0.57 0.022 g 1.77 1.9 2.03 0.070 0.075 0.080 g1 26.77 1.054 h1 29.00 1.142 h2 28.00 1.102 h3 17.00 0.669 h4 0.80 0.031 l 19.05 19.95 0.75 0.785 l1 1.10 1.40 0.043 0.055 l2 2.60 2.90 0.102 0.114 l3 15.35 15.65 0.604 0.616 n1 10 0.394 n3 6.8 0.268 n4 3.8 0.15 dia1 13.00 0.511 h1 h2 h3 dia.2 dia.4 h4 n1 n4 dia.3 l3 n3 g g1 d d f1 l1 l2 dia.1 a e b l flex15 b1 f l3000s - l3030 26/29
powerso-20 (slug-up) package mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.70 0.145 a1 0 0.25 0 0.01 b 0.40 0.53 0.016 0.021 c 0.23 0.32 0.009 0.012 d 15.80 16.00 0.622 0.63 d1 9.4 9.80 0.37 0.385 e 13.90 14.50 0.547 0.57 e 1.27 0.05 e3 11.43 0.45 e1 10.90 11.10 0.429 0.437 e2 2.90 0.114 e3 5.80 6.20 0.228 0.244 g 0 0.10 0 0.004 h 1.10 0.043 l 0.80 1.10 0.031 0.043 n 10 (max.) s 8 (max.) e a e a1 pso20dme d e1 e2 hx45 s gage plane 0.35 l detaila detaila (coplanarity) gc -c- seating plane e3 b c n n e3 (slug width) 10 1 d1(slug width) 20 11 l3000s - l3030 27/29
powerso20 (slug-down) package mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039 b 0.40 0.53 0.0157 0.0209 c 0.23 0.32 0.009 0.0126 d (1) 15.80 16.00 0.6220 0.6299 e 13.90 14.50 0.5472 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.90 11.10 0.4291 0.437 e2 2.90 0.1141 g 0 0.10 0 0.0039 h 1.10 l 0.80 1.10 0.0314 0.0433 n 10 (max.) s 8 (max.) t 10.0 0.3937 (1) od and e1o do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006o) e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 hx45 detail a lead slug a3 s gage plane 0.35 l detailb r detail b (coplanarity) gc -c- seating plane e3 b c n n l3000s - l3030 28/29
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rig hts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics printed in italy all rights reserved powerso-20 ? is a trademark of the sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. l3000s - l3030 29/29

▲Up To Search▲

Price & Availability of L3000SX-77

	To Download L3000SX-77 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .